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FUJITSU SEMICONDUCTOR
FR50 32-BIT MICROCONTROLLER MB91F367GA/F368GA Datasheet
Release 1.0 10-Apr-2001
Revision History
Revision 1.0
Date 10-Apr-2001
Item First revision of preliminary datasheet for MB91F367GA and MB91F368GA
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Table of Contents
1 MB91F367GA/F368GA Overview . . . . . . . . . . . . . . . . . . . . . . 5 1.1 MB91F367GA Block Structure . . . . . . . . . . . . . . . . . . . . . . 6 1.2 MB91F368GA Block Structure . . . . . . . . . . . . . . . . . . . . . . 7 1.3 Core Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5 Pin Assignment MB91F367GA . . . . . . . . . . . . . . . . . . . . . 14 1.6 Pin Assignment MB91F368GA . . . . . . . . . . . . . . . . . . . . . 15 1.7 I/O Pins and Their Functions . . . . . . . . . . . . . . . . . . . . . . . 16 1.8 Flash Memory Mode of MB91F367GA/F368GA . . . . . . . 20 2 Additional information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.1 Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.1.1 Flash Control Status Register (FMCS) . . . . . . . . . . . . . . . 22 2.1.2 Flash Wait Control Register (FMWT) . . . . . . . . . . . . . . . 23 2.2 F362 Mode Register (F362MD) . . . . . . . . . . . . . . . . . . . . . 27 2.3 Oscillation stabilization time . . . . . . . . . . . . . . . . . . . . . . . 28 2.4 Subclock RTC32 (CLKR2) . . . . . . . . . . . . . . . . . . . . . . . . 28 2.5 Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3 IO-Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4 Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 Power-on-sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 Handling of Unused Input Pins . . . . . . . . . . . . . . . . . . . . . . . . 30 7 Emulation Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . 33 9.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.3 Run Mode Current/Power consumption . . . . . . . . . . . . . . . 36 9.3.1 Logic Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . 36 9.3.2 Analog Power Consumption . . . . . . . . . . . . . . . . . . . . . . 37 9.3.3 I/O and SMC Power Consumption . . . . . . . . . . . . . . . . . . 37 9.4 Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.5 Clock settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.6 Clock modulator settings . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Appendix A I/O Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Appendix B Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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CHAPTER 1
MB91F367GA/F368GA Overview
This device is available in two options. The difference between these options is as follows:
Feature
MB91F367GA
MB91F368GA
RTC module
connected to 4 MHz oscillator
connected to 32kHz oscillator at pins 27, 28 calibration unit available
See the following chapters for more details:
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1.1
MB91F367GA Block Structure
4 MHz Oscillator Clock Modulator User RAM 16 KB Bit Search Module Boot ROM 2KB F-bus RAM 16 KB Flash Memory 512 KB R-Bus Adapter
SIO Prescaler/ SIO (2ch)
16 32
FR50 Core
Watchdog Timer
32
Instruction RAM 4KB
32
Bus Converter
DMA Controller
32
User Logic Bus Interface
External Interrupt (8 ch)
CAN (2ch)
ADC (8 ch)
U-Timer/ UART (1ch)
I2C
Reload Timer (3ch)
Alarm Comparator
RTC
Power down Reset
ICU (4 ch)
Free Running Counter (2 ch)
OCU (2 ch)
Voltage regulator
Prog. Pulse Generator (4ch)
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1.2
MB91F368GA Block Structure
4 MHz Oscillator Clock Modulator User RAM 16 KB Bit Search Module Boot ROM 2KB F-bus RAM 16 KB Flash Memory 512 KB R-Bus Adapter
SIO Prescaler/ SIO (2ch)
16 32
FR50 Core
Watchdog Timer
32
Instruction RAM 4KB
32
Bus Converter
DMA Controller
32
User Logic Bus Interface
External Interrupt (8 ch)
CAN (2ch)
ADC (8 ch)
32kHz Subclock Calibration unit
U-Timer/ UART (1ch)
I2C
Reload Timer (3ch)
Alarm Comparator
RTC
Power down Reset
ICU (4 ch)
Free Running Counter (2 ch)
OCU (2 ch)
Voltage regulator
Prog. Pulse Generator (4ch)
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1.3
Core Functionality
Function FR50 Core FR30 software compatible Setting of frequencies for CPU and peripherals (see MB91FV360GA) Feature 32-bit Fujitsu RISC Core Remarks
Clock module (clock control, clock divider, PLLs)
Low power consumption modes: RTC mode: only the Real Time Clock and the selected oscillator are active (= STOP mode and bit 0 of STCR is set to 0) STOP mode: all internal circuits and the oscillation circuits are halted adjustable watchdog timer interval (between 220 and 226 system clock cycles) I-RAM RAM for user data RAM for data and code sector architecture: sector 0: 64 kB sector 1: 64 kB sector 2: 64 kB sector 3: 32 kB sector 4: 8 kB sector 5: 8 kB sector 6: 16 kB | V 16 bit | sector 7: 64 kB | sector 8: 64 kB | sector 9: 64 kB | sector 10: 32 kB | sector 11: 8 kB | sector 12: 8 kB | sector 13: 16 kB | V 16 bit connected to F-Bus Minimum 10000 program/erase cycles Minimum 10 years data retention see remark below table see remark below table see remark below table
Watchdog
I-RAM 4 kB D-bus RAM 16 kB F-bus RAM 16 kB
Flash Memory 512 kB
Net read cycle time to the memory is 40nS. For overall access time see settings in Chapter 2.1
write access is 16 bit wide, read access can be 16 or 32 bit wide Boot ROM 2 kB 5 channels up to 16 DMA sources can be used DMA transfer modes: single/block, burst, continuous
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Interrupt Controller
8 external interrupt channels, 38 internal interrupts, 16 programmable priority levels Searches a word for the position of the first "1" and "0" change bit, starting from the MSB. Performs the search in 1 cycle. Hardwired reset and mode vector Generates internal voltage of 3.3 V Code start at 0F:4000H
Bit Search Module Fixed Reset Vector Voltage Regulator
Remark: Set bit 9 (SYNCR) of TBCR to 1 to enable the synchronisation of the reset signal; a reset will be generated only after all bus accesses have been done. This avoids that erroneous data are written into the RAMs during reset.
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1.4
Features
Function Feature 16-bit PWM Timer 16 bit down counter, cycle and duty setting registers interrupt at triggering, cycle or duty match can be triggered by software or reload timer PWM operation and one-shot operation Clock disable internal prescaler allows fRES/1, fRES/4, fRES/16, fRES/64 as counter clock successive approximation, internal sample and hold circuit 10-bit resolution, 5 V operation, (conversion time: 178 cycles of CLKP) program selectable analogue input channels: single conversion mode continuous conversion mode stop conversion mode interrupt at the end of a conversion can be used to activate DMA transfer activation by software Prescaling is done internally Clock disable Basic Interval Timer (3 channels) 16-bit reload timer, includes clock prescaler (fRES/21, fRES/23, fRES/25) conforms to CAN specification version 2.0 A and B automatic re-transmission in case of error automatic transmission responding to remote frame prioritized 16 message buffers for data and IDs supports multiple messages flexible configuration of acceptance filtering: full bit compare / full bit mask / two partial bit masks supports up to 1 Mb/s Clock Disable required frequencies are 90-300 Hz Remarks
PPG for dimmer (4 channels)
ADC (8 channels)
CAN (2 channels)
CAN allows TSEG2 = RSJW setting
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External Interrupt (8 channels) I2C-1 for standard mode
can be programmed to be edge sensitive or level sensitive interrupt masking and request pending bits per channel master or slave transmission arbitration function clock synchronization function slave address and general call address detect function transfer direction detect function start condition repeat generation and detection function bus error detect function compatible to I2C standard mode specification (operation up to 100 kHz, 7 bit addressing) includes clock divider functionality
Only I2C-1 or I2C-2 can be used, not both in parallel. Bit 0 of F362MD will be used to decide which module is connected to the SCL and SDA pads. By default it is I2C-1.
I2C-2 for standard and fast mode
Clock disable master or slave transmission arbitration function clock synchronization function slave address and general call address detect function transfer direction detect function start condition repeat generation and detection function bus error detect function compatible to I2C standard and fast mode specification (operation up to 400 kHz, 10 bit addressing) includes clock divider functionality
Only I2C-1 or I2C-2 can be used, not both in parallel. Bit 0 of F362MD will be used to decide which module is connected to the SCL and SDA pads. By default it is I2C-1.
SCL and SDA lines include optional noise filter. The noise filter allows the suppression of spikes in the range of 1 to 1.5 cycles of CLKP . Communication on the I2C bus between other connected devices is not possible if MB91F36xGA is not connected to the power supply.
Clock disable rising edge, falling edge or rising & falling edge sensitive two 16-bit capture registers signals an interrupt at external event Clock disable signals an interrupt when a match with of 16-bit IO timer occurs an output signal can be generated Clock disable
16-bit Input Capture (ICU) (4 channels) 16-bit Output Compare OCU (2 channels)
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Free running Timer (2 channels for ICU and OCU modules)
16-bit free running timer, signals an interrupt when overflow or match with compare register_0 includes prescaler (fRES/22, fRES/24, fRES/ 25, fRES/26) timer data register has R/W access Clock disable monitors an external voltage and generates an interrupt in case of a voltage lower or higher than the defined thresholds status is readable, interrupts can be masked separately Clock disable monitors Vdd and generates a reset if Vdd is less than a defined threshold voltage Serial IO transfer can be started from MSB or LSB supports internal clock synchronized transfer and external clock synchronized transfer prescaler for shift clock allows: fRES/3, fRES/4, fRES/5, fRES/6, fRES/7, fRES/8 Clock disable
Alarm Comparator (OV/UV detection)
uses external 4:1 voltage divider
Power down reset
disabled in RTC and STOP modes
Serial IO SIO Synchronous Serial Interface (2 channels) + SIO-Prescaler (2 channels)
supports positive and negative clock edge synchronization
UART (1 channel)
serial I/O port for performing asynchronous (start-stop synchronization) communication full duplex, double buffering supports multi-processor mode variable data length (7/8 bit) 1 or 2 stop bits error detection function (parity, framing, overrun) interrupt function NRZ type transfer format baud rate generated by U-Timer 16-bit timer to generate the required UART clock: fRES/25,...,~fRES/221 (asynchr. mode) Clock disable
polarity of the port signals for receive and transmit is programmable
U-Timer (1 per UART)
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facility to correct oscillation deviation read/write accessible second/minute/ hour registers can signal interrupts every second/ minute/hour/day Real Time Clock (RTC) (Watch Timer) internal clock divider and prescaler provide exact 1s clock this clock is based on the 4 MHz oscillator or if the subclock option is selected on the 32 kHz subclock Clock disable In RTC mode, the RTC module can be driven by either 4MHz or 32KHz oscillator, depending on the configuration. Additional hardware which allows calibration of the 32KHz clock based on the 4MHz clock is built in. This function is only available on MB91F368GA.
prescaler values are 1E847FH , and 4000H for 4MHz and 32.768KHz respectively.
32KHz subclock + calibration unit
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1.5
Pin Assignment MB91F367GA
Digital I/O-Ports
UART
CAN
PWM
SIO
91
PG3 PG4 PG5 VDD VSS PR0 PR1 PR2 PR3 VDD PR4 PR5 PR6 PR7 VSS PS0 PS1 PS2 PS3 VDD PS4 PS5 PS6 PS7 VSS VDD PJ0 PJ1 PJ2 PJ3 INITX MD2 MD1 MD0 VDD OUT1 OUT0 IN3 IN2 IN1 IN0
PG2 PG1 PG0 PQ3 PQ2 SOT0 SIN0 Vss VDD RX1 TX1 RX0 TX0 PO7 PO6 PO5 PO4
90
OCPA3 OCPA2 OCPA1 OCPA0 Vss SCK3 SOT3 SIN3 SCK4 SIN4 SOT4 Vss VDD
61
60
OCU
ICU
MB91F367GA 120-pin plastic QFP no subclock
Vss VCC3C VDD INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 MONCLK
ext. Int.
INDEX
Vss X1 4 MHz Osc. X0 VDD CPUTESTX TESTX BOOT
120
31
1
AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 NC NC ALARM Vss
VDD Vss AVRH AVCC
VDD Vss
PJ4 PJ5 PJ6 PJ7
PI3 VDD Vss
PM0
PM1 SDA SCL
30
Digital IO-Ports
IC
2
ADC
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1.6
Pin Assignment MB91F368GA
Digital I/O-Ports
UART
CAN
PWM
SIO
PG2 PG1 PG0 PQ3 PQ2 SOT0 SIN0 Vss VDD RX1 TX1 RX0 TX0
91
PG3 PG4 PG5 VDD VSS PR0 PR1 PR2 PR3 VDD PR4 PR5 PR6 PR7 VSS PS0 PS1 PS2 PS3 VDD PS4 PS5 PS6 PS7 VSS VDD PJ0 PJ1 PJ2 PJ3
Vss SCK3 SOT3 SIN3 SCK4 SIN4 SOT4 Vss VDD
90
PO7 PO6 PO5 PO4
OCPA3 OCPA2 OCPA1 OCPA0
61
60
INITX MD2 MD1 MD0 VDD OUT1 OUT0 IN3 IN2 IN1 IN0 Vss VCC3C VDD INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 MONCLK Vss X1 4 MHz Osc. X0 VDD CPUTESTX TESTX BOOT
OCU
ICU
MB91F368GA 120-pin plastic QFP subclock
ext. Int.
INDEX
120
AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 X0A
31
VDD Vss
VDD Vss AVRH AVCC
PI3 VDD Vss
PM1 SDA SCL
PJ4 PJ5 PJ6 PJ7
1
X1A ALARM Vss
PM0
30
Digital IO-Ports
I2 C
ADC
32KHz Osc.
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1.7
I/O Pins and Their Functions
Table 1.7a Pinning
Pin No. QFP120
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Pin Name
VDD VSS PJ4 PJ5 PJ6 PJ7 PI3 VDD VSS PM0 PM1 SDA SCL VDD VSS AVRH AVCC AVSS/AVRL AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 X0A N.C. X1A N.C. ALARM VSS BOOT TESTX CPUTESTX VDD X0 X1 VSS MONCLK INT0 INT1 INT2 INT3
General Circuit I/O Purpose Type I/O Port
Function
I/O I/O I/O I/O I/O
PJ4 PJ5 PJ6 PJ7 PI3
A A A A A
Digital IO-Port Digital IO-Port Digital IO-Port Digital IO-Port Digital IO-Port
I/O I/O I/O I/O
PM0 PM1 PM2 PM3
A A Y Y
Digital IO-Port Digital IO-Port I2C SDA (no internal pull-up!) I2C SCL (no internal pull-up!)
R
I/O I/O I/O I/O I/O I/O I/O I/O I O I I/O I I I O O I/O I/O I/O I/O
PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7
B B B B B B B B I I D
Analog Voltage Ref. high Analog VCC Ana.Volt.Ref.low/An.VSS ADC input ADC input ADC input ADC input ADC input ADC input ADC input ADC input 32 KHz Oscillator Pin (MB91F368GA) not connected (MB91F367GA) 32 KHz Oscillator Pin (MB91F368GA) not connected (MB91F367GA) Alarm Comparator Input BOOT pin Test mode pin Test mode pin 4 MHz Oscillator Pin 4 MHz Oscillator Pin Clock output Ext. Interrupt Ext. Interrupt Ext. Interrupt Ext. Interrupt 10-Apr-01
P93
A E E H H G A A A A
PK0 PK1 PK2 PK3
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Table 1.7a Pinning
Pin No. QFP120
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89
Pin Name
INT4 INT5 INT6 INT7 VDD VCC3/C VSS IN0 IN1 IN2 IN3 OUT0 OUT1 VDD MD0 MD1 MD2 INITX VDD VSS SOT4 SIN4 SCK4 SIN3 SOT3 SCK3 VSS OCPA0 OCPA1 OCPA2 OCPA3 PO4 PO5 PO6 PO7 TX0 RX0 TX1 RX1 VDD VSS SIN0 SOT0 PQ2 PQ3 PG0 PG1
General Circuit I/O Purpose Type I/O Port
I/O I/O I/O I/O PK4 PK5 PK6 PK7 A A A A A
Function
Ext. Interrupt Ext. Interrupt Ext. Interrupt Ext. Interrupt supply pin for internal voltage regulator Capacitor pin for V. reg. ICU input ICU input ICU input ICU input OCU Output OCU Output supply pin for internal voltage regulator Mode Pin Mode Pin Mode Pin Initial supply pin for internal voltage regulator SIO output SIO input SIO clock SIO input SIO output SIO clock PPG output PPG output PPG output PPG output Digital IO-Port Digital IO-Port Digital IO-Port Digital IO-Port CAN TX output CAN RX output CAN TX output CAN RX output
I/O I/O I/O I/O I/O I/O I I I I
PL0 PL1 PL2 PL3 PL4 PL5
A A A A A A T T T U
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
PN0 PN1 PN2 PN3 PN4 PN5 PO0 PO1 PO2 PO3 PO4 PO5 PO6 PO7 PP0 PP1 PP2 PP3
A A A A A A A A A A A A A A Q Q Q Q
I/O I/O I/O I/O I/O I/O
PQ0 PQ1 PQ2 PQ3 PG0 PG1
A A A A A A
UART input UART output Digital IO-Port Digital IO-Port Digital IO-Port Digital IO-Port 10-Apr-01
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Table 1.7a Pinning
Pin No. QFP120
90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Pin Name
PG2 PG3 PG4 PG5 VDD VSS PR0 PR1 PR2 PR3 HVDD PR4 PR5 PR6 PR7 VSS PS0 PS1 PS2 PS3 HVDD PS4 PS5 PS6 PS7 VSS VDD PJ0 PJ1 PJ2 PJ3
General Circuit I/O Purpose Type I/O Port
I/O I/O I/O I/O PG2 PG3 PG4 PG5 A A A A
Function
Digital IO-Port Digital IO-Port Digital IO-Port Digital IO-Port
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
PR0 PR1 PR2 PR3 PR4 PR5 PR6 PR7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7
K1 K1 K1 M1 K1 K1 K1 M1 K1 K1 K1 M1 K1 K1 K1 M1
Digital IO-Port Digital IO-Port Digital IO-Port Digital IO-Port VDD for ports R and S Digital IO-Port Digital IO-Port Digital IO-Port Digital IO-Port Digital IO-Port Digital IO-Port Digital IO-Port Digital IO-Port VDD for ports R and S Digital IO-Port Digital IO-Port Digital IO-Port Digital IO-Port
I/O I/O I/O I/O
PJ0 PJ1 PJ2 PJ3
A A A A
Digital IO-Port Digital IO-Port Digital IO-Port Digital IO-Port
Remark: Pin 31 (BOOT) should be low by default (pull down resistor). To avoid disturbances in case of reset/boot it should preferably only be used as output by any application.
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Table 1.7b Circuit Types
Circuit Type
A B D E G H I K1 M1 Q R T U Y
Description
I/O, IOH=4 mA / IOL=4 mA, CMOS Automotive Schmitt-Trigger Input, STOP control I/O, IOH=4 mA / IOL=4 mA, CMOS Automotive Schmitt-Trigger Input, Analog Input, STOP control Analog Input CMOS Schmitt-Trigger Input, 50K Pull-up Tristate Output, IOH=4 mA / IOL=4 mA 4 MHz Oscillator Pin 32KHz Oscillator Pin I/O, IOH=30 mA / IOL=30 mA, CMOS Automotive Schmitt-Trigger Input, STOP control I/O, IOH=30 mA / IOL=30 mA, CMOS Automotive Schmitt-Trigger Input, Analog Input, STOP control I/O, IOH=4 mA / IOL=4 mA, CMOS Input, STOP control AVRH Input CMOS Input, can withstand VID for flash programming CMOS Schmitt-Trigger Input, 50K Pull-up I/O, IOH=3mA / IOL=3mA (I2C), CMOS Input, STOP control
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1.8
Flash Memory Mode of MB91F367GA/F368GA
To enter the flash memory mode set mode pins MD0 to MD2 to "111". Assert INITX for at least 500 ns to enter this mode. The following tables show the pins which are required for the programming procedure and also describe the states for the pins not used in flash memory mode. Most of the not used pins are in their reset state (high-Z outputs, enabled inputs). To prevent misbehavior or damage these pins must be tied to VDD or VSS through resistors - see following tables for details. Aside from the functional pins described below all power pins should be connected to a power supply in the specified range, capacitances should be connected to the VCC3C pin as recommended.
Table 1: Flash Control Signals MB91F367GA/F368GA MBM29LV400C Pin number
31 32 33 38 39-46 50 51 52 53 54 55 57 58 59 60 91-93 96 97 98 99
Notes
Normal function
BOOT TESTX CPUTESTX MONCLK INT0-INT7 IN0 IN1 IN2 IN3 OUT0 OUT1 MD0 MD1 MD2 INITX PG3-PG5 PR0 PR1 PR2 PR3
Flash Memory mode
WE BYTE TMODX RY/BY D24 to D31 CE OE D20 D21 D22 D23 VDA9 VDRS VDOE RESET A16-A18 A0 A1 A2 A3 RY/BY DQ8 to DQ15 CE OE DQ4 DQ5 DQ6 DQ7 A9 (VID) RESET (VID) OE (VID) RESET A15-A17 A-1 A0 A1 A2 10-Apr-01 WE BYTE pull up
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Table 1: Flash Control Signals MB91F367GA/F368GA MBM29LV400C Pin number
101 102 103 104 106 107 108 109 111 112 113 114 117 to 120
Notes
Normal function
PR4 PR5 PR6 PR7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PJ0-PJ3
Flash Memory mode
A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D16 to D19 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 DQ0 to DQ3
Table 2: Pins not used in Flash Memory Mode MB91F367GA/F368GA Pin number
35 36 66 67 68 27 28 29
Normal function
X0 X1 SIN3 SOT3 SCK3 X0A X1A ALARM
Pin State
input output output output output input output input input
Notes
pull up leave open leave open leave open leave open pull up leave open pull up pull up
all other signals
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CHAPTER 2
2.1
Additional information
Flash Interface
2.1.2 Flash Control Status Register (FMCS)
address 00007000H access initial value value after Boot ROM bit 7 FACCEN R/W 1 0 bit6 ---R/W 1 1 bit 5 ---R/W 1 1 bit 4 RDYEG R 0 0 bit 3 RDY R X X bit 2 RDYI R/W 0 0 bit 1 WE R/W 0 0 bit 0 LPM R/W 0 0
Bit 7: FACCEN: Controls read access mode to flash 0: Synchronous read access using ATDIN and EQIN signals - recommended setting 1: Asynchronous read access Bits 6,5: reserved when writing to these bits always write "11" Bit 4: RDYEG: When the auto algorithm of flash memory is finished, this bit is set to '1'. This bit is cleared by reading it. 0: Auto algorithm not yet finished 1: Auto algorithm finished Bit 3: RDY: The state of auto algorithm 0:The state of the auto algorithm is WRITE/READ. Can't accept WRITE/READ/DELETE. 1:It is possible to accept WRITE/READ/DELETE. Bit 2: RDYI: Reserved bit Bit 1: WE: This bit is used to control writing and reading to flash memory in CPU mode 0: writing to flash memory is disabled, read access is 32 bit wide 1: writing enabled, read access 16 bit wide, auto algorithm can be used This bit can only be written to if RDY is 1. Bit 0: LPM: 0: normal mode 1: low power mode, can be used when CPU frequency is below 5 MHz FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 22 10-Apr-01
2.1.3 Flash Wait Control Register (FMWT)
address 0000700 4H access initial value value after Boot ROM bit 7 ---bit6 ---R/W 0 bit 5 FAC1 R/W 0 bit 4 FAC0 R/W 0 bit 3 EQINH R/W 0 bit 2 WTC2 R/W 0 bit 1 WTC1 R/W 1 bit 0 WTC0 R/W 1
0
0
1
0
0
1
1
Bit 6: This bit is reserved, always set this bit to "0" when writing to this register. Bits 5,4: These bits control the length of the high pulse for the ATDIN signal
FAC1
FAC0
length of high pulse for ATDIN
0 0 1 1
0 1 0 1
0.5 cycles of CLKB 1 cycle of CLKB 1.5 cycles of CLKB 2 cycles of CLKB
Bit 3: EQINH: This bit controls the falling edge of the EQIN signal. 0: falling edge of EQIN at falling edge of FWAITR; 1: falling edge of EQIN half cycle after falling edge of FWAITR; Bit 2,1,0: WTC2,1,0: Wait Cycle bits WTC2-0 are used to insert auto wait cycles for flash memory access.
WTC2
WTC1
WTC0
wait cycles
0 0 0 0 1
0 0 1 1 0
0 1 0 1 0
0 1 2 3 4 10-Apr-01
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 23
WTC2
WTC1
WTC0
wait cycles
1 1 1
0 1 1
1 0 1
5 6 7
Recommended settings for FAC1, FAC0 and WTC2 to WTC0 for read access to the flash memory: * Without applying clock modulation:
CLKB unmodulated core clock frequency [MHz]
FAC1
FAC0
EQINH
WTC2
WTC1
WTC0
ATDIN high cycles/wait cycles
FMWT
32 24 16
0 0 0
0 0 0
1 0 0
0 0 0
0 0 0
1 1 1
0.5 / 1 0.5 / 1 0.5 / 1
09H 01H 01H
*
When applying clock modulation:
CLKB core clock frequency [MHz]
Peak max. frequency
FAC1
FAC0
EQINH
WTC2
WTC1
WTC0
ATDIN high cycles/wait cycles
FMWT
32 32 24 24 16
64 48 40 32 24
0 0 0 0 0
1 0 0 0 0
0 0 0 1 0
0 0 0 0 0
1 1 1 0 0
1 0 0 1 1
1/3 0.5 / 2 0.5 / 2 0.5 / 1 0.5 / 1
13H 02H 02H 09H 01H
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 24
10-Apr-01
Example for flash memory read access with 1 cycle for the high time of ATDIN and 3 wait cycles: 1 cycle ATDIN high 3 wait cycles
CLKB
core clock
FA
A1
A2
A3
F-bus address F-bus wait ATDIN for flash
FWAITR
ATDIN tWATD
EQIN FD tACC
EQIN
tWEQ D1
for flash F-bus data
tRC
The minimum value for tWATD is 10 ns, the minimum value for tWEQ is 20 ns. The minimum value for tRC is 40 ns. The maximum value for tACC is tWATD+tWEQ+5 ns.
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 25
10-Apr-01
Recommended settings for WTC2 to WTC0 for write access to the flash memory, FACCEN of FMCS should be set to 1 for writing, so FAC1, FAC0, EQINH register settings then have no meaning for the write operation : * Without applying clock modulation:
CLKB unmodulated core clock frequency [MHz]
WTC2
WTC1
WTC0
Wait cycles
FMWT
32 24 16
0 0 0
1 1 0
0 0 1
2 2 1
X2H X2H X1H
*
When applying clock modulation:
CLKB core clock frequency [MHz]
Peak max. frequency
WTC2
WTC1
WTC0
Wait cycles
FMWT
32 32 24 24 16
64 48 40 32 24 1 1 0 0 0 0 1 1
setting not allowed for writing 0 0 0 0 4 4 2 2 X4H X4H X2H X2H
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 26
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2.2
address
F362 Mode Register (F362MD)
bit 15 ---bit14 --R/W 0 bit 13 ---R/W 0 bit 12 ---R/W 0 bit 11 ---R/W 0 bit 10 ---R/W 0 bit 9 ---R/W 0 bit 8 IICSEL R/W 0
00001FEH access initial value Bit 15-9:
reserved, when writing to bits 15-9, always write "0000000"
Bit 8:
IICSEL 0: selection of 100 kHz I2C interface (I2C-1) 1: selection of 400 kHz I2C interface (I2C-2)
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 27
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2.3
Oscillation stabilization time
For a mode setting of MD[2:0] = "000" the following settings of OS1 and OS0 bits in the standby control register (STCR) will be implemented:
OS1
OS0
Oscillation stabilization wait time
time based on 4 MHz oscillator ()
0 0 1 1
0 1 0 1
* 216 * 211 * 216 * 21
32 ms (initial value) 1 ms 32 ms 1 s
2.4
Subclock RTC32 (CLKR2)
bit 15 ---bit14 ---bit 13 ---bit 12 ---bit 11 ---bit 10 ---R/W 0 bit 9 ---R/W 0 bit 8 RTC32 R/W 0
This register is used to control the RTC32 mode bit for use in subclock system. address 000046H access initial value Bit [15:11]: reserved Bit [10:9]: Bit 8: reserved, always write 0 back when writing to these bits. RTC32 0: RTC32KHI mode, high power mode of internal voltage regulator used in RTC mode 1: RTC32KLO mode, low power mode of internal voltage regulator used in RTC mode Always set this bit to 1 when using the RTC mode based on the 32 kHz subclock. This is only available for MB91F368GA.
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2.5
* * * * * *
Boot ROM
Flash area: 08:0000 to 0F:FFF7 Security Vector at 0F:FEF4 Security vector valid in ranges 08:0000-0F:FFFF Program entry at 0F:4000 ROM stamp at 05:0500 Flash registers initialized to FMCS=0x60, FMWT=0x13
The following settings have been implemented in the BOOT ROM of MB91F367GA/F368GA:
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 29
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CHAPTER 3
see appendix A.
IO-Map
The addresses shown in this table for CAN registers are based on the settings for CS7 done in the Boot ROM.
CHAPTER 4
see appendix B .
Interrupt Vector Table
CHAPTER 5
Power-on-sequence
All VDD pins should be connected to the same potential. The analogue supply voltage (AVCC) must not be turned on before the digital supply voltage. Immediately after power on always execute INIT at the INITX pin (input a low level to the INITX pin). Hold this low level at the INITX pin long enough so that after release of the low level at INITX and the passing of the built in waiting time stable oscillation of the oscillation circuit is achieved. INITX must be pulled low for at least 8 cycles of the 4 MHz oscillation clock.
CHAPTER 6
Handling of Unused Input Pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefore they must be tied to VDD or VSS through resistors. In this case those resistors should be more than 2 KOhm. Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. The resistor of more than 2 KOhm is used to limit currents through the protection diodes. In case of voltages at the unused pin of 0.3 V or more below VSS or 0.3 V or more above VDD currents which could cause latch-up will flow through those diodes. It is possible to use one resistor to connect several pins to VDD or VSS. Care should be taken not to connect pins from different supply voltage domains to one resistor.
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 30
10-Apr-01
CHAPTER 7
Emulation Device
MB91FV360GA can be used as an emulation device for MB91F367GA/F368GA. MB91F367GA/F368GA use the following resources of MB91FV360GA (see MB91FV360GA IO-Map): * * * * * * * * * * * * * * * * * Reload Timer 0 - Reload Timer 2 UART 0 / U-Timer 0 SIO 0 - SIO 1 and their Prescalers I2C (100KHz and 400KHz) A/D Converter (channels 0 - 7) Input Capture 0 - Input Capture 3 Output Compare 0 - Output Compare 1 Free Running Counter 0 - Free Running Counter 1 Real Time Clock 32 kHz subclock and calibration unit - MB91F368GA only Programmable Pulse Generators: PWM Control 0, PWM channels 0 - 3 Power down reset Alarm Comparator CAN0 - CAN 1 User RAM 16KB: address range: 03C000-03FFFF F-Bus RAM 16KB: address range: 040000-043FFF I-RAM 4KB: address range: 011000-011FFF
Note: Because reload timers 3 to 5 are not available on this device, the ADC cannot be triggered by a reload timer - on MB91FV360GA and other devices reload timer 4 is connected to the ADC
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 31
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CHAPTER 8
Package
A QFP-120 package called FPT-120P-M21 (0.5 mm pin pitch) will be used for MB91F367GA/F368GA. The thermal resistance of this package is 30 degr. C/W.
Thermal resistance [degr. C/W]
theta-ja (junction to ambient) 0 m/s 30 1 m/s 27 3 m/s 25
theta-jc (junction to case)
5
The maximum allowed ambient temperature is 85 degr. C, the maximum allowed junction temperature is 125 degr.C. Under these conditions a maximum power consumption of (125 degr. C - 85 degr. C) / 30 C/W = 1.33 W is allowed. The user must make sure that the maximum ambient temperature is not exceeded. For other details about the package see Fujitsu Semiconductor Package Data Book.
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CHAPTER 9
9.1
Electrical specification
Absolute maximum ratings
Symbol
VDD-VSS
Parameter Digital supply voltage Storage temperature Power consumption Digital input voltage Analog input voltage Analog supply voltage Analog reference voltage
ST PTOT VIDIG VIA
VDDA-VSSA
min. -0.3 -55 -0.3 * -0.3 -0.3 -0.3 -2
max. 6.0 125 1330 5.8 5.8 5.8 5.8 2
Unit V C mW V V V V mA
Condition
ambient = 25C VSS=0V, VDD=5V VSSA=0V, VDDA=5V VSSA=0V VSSA=0V
VREFH/L VSSA
Static DC current into digital I/O
II/ODC
II/ODC < ISoperation
* Making full use of the allowed static DC current into digital I/Os will lead to lower values here.
9.2
Parameter Operating temperature Supply voltage - Digital supply - Analog supply
Operating conditions
Symbol OP
VDD-VSS
min. -40 4.25
1)
typ.
max. 85 5.25
Unit C V
Condition
Internal voltage reg. VDDCORE=3.3V
5
VDDA-VSSA
4.9
5 see 0.5 TBD 10
5.1 below 1.25 0.5 200
V mA mA m A V
VSSA=0V
Current consumption -run mode 3) -RTC mode
Isrun IsRTC4 IsRTC32 Isstop VDD-VSS 3.0
fclk=4MHz@op=25C fclk=32KHz@op=25C
-stop mode RAM data retention voltage
fclk =0 @op=25C
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Alarm comparator -Threshold voltages - overvoltage - undervoltage
VTAH VTAL
4
/5 VDDA -5% /5 VDDA -5%
4
/5VDDA
4
/5 VDDA +5% /5 VDDA +5%
V V
(external 4:1 divider)
2
2
/5VDDA
2
- Switching hysteresis - Alarm sense time - Input resistance Power down Reset -Threshold voltage - Switching hysteresis - Reset sense time Digital Inputs 2) CMOS (Type:Q) - High voltage range - Low voltage range CMOS Schmitt-Trigger (Types: E, U) - High voltage range - Low voltage range CMOS Automotive Schmitt-Trigger (Types: A, B, W, X) - High voltage range - Low voltage range - Hysteresis voltage - Input capacitance - Input leakage current - Pull up resistor Digital outputs - Output "H" voltage - Output "L" voltage
V TAHYS tAS Rin VTPOR VTPORHYS tRS
12.5
25
50 10
mV
at VTAH, VTAL
s M
5 3.5 20 4.0 50 4.5 80 10
V mV s
VIH VIL
0.65*VDD
VSS
VDD 0.25*VDD
V V
VIH VIL
0.8*VDD
VSS
VDD 0.2*VDD
V V
VIH VIL
0.8*VDD
VSS 0.5
VDD 0.5*VDD 0.6*VDD
V V V V pF A k
Vmin=4.25V Vmin=4.75V
CIN IIL Rup1 VOH VOL
-1 50 VDD-0.5 VSS
16 1
Types: E, U
op=25C
VDD VSS+0.4
V V
Iload = 4mA Iload = - 4mA
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 34
10-Apr-01
ADC inputs 4) - Reference voltage input - Input voltage range - Input resistance - Input capacitance - Impedance of external output driving the ADC input - Input leakage current
VREFH VREFL Vimax Vimin RI CI
VREFL+3 VSSA
VDDA VREFH-3 VREFH
V V V V k pF k
RI
VREFL 3.6 30 4.0
CI
@ sampling time of 1.6 s
IIL
-1
1
A
op=25C
PPG - Output voltage - Output current I2C Bus Interface - Output voltage - Output current - Input threshold voltage Lock-up time PLL1 (4MHz->16...64MHz) ESD Protection (Human body model MIL883-B compliant)
1)
VoutHIGH VoutLOW Iout
VDD-0.5 VSS 4
VDD VSS+0.4
V V mA
Open Drain Output
VoutHIGH VoutLOW Iout VIH VIL
VSS 3
0.65*VDD
VDD VSS+0.4
V V mA V V ms kV
IoutLOW= 3mA
VSS
VDD 0.25*VDD 1
Vsurge
2
Rdischarge=1.5k Cdischarge= 100pF
this is only valid if the integrated power-down reset circuit is switched-off, else a reset can be triggered at voltages less or equal than 4.5 V (see spec items for power-down reset) 2) valid for bidirectional tristate I/O PAD cell 3) IISRUN describes the current consumption of the MCU core only and has been determined by setting the clock frequencies shown below and running an endless loop from internal flash memory which generates activity on all internal buses. A procedure to calculate the overall power consumption is also shown below.
4)
The protection diodes at the analog inputs are connected to the digital supply voltage
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 35
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9.3
Run Mode Current/Power consumption
The power dissipation during normal operation is determined by the total power dissipation of the internal logic PC, the dissipation from analog modules PA and the power dissipation PIO of the I/O buffers. Among the I/O buffers the dissipation caused by the stepper motor drivers PSMC should be taken into special consideration. So the overall power consumption PD will be calculated as a sum of Pc + PA + PIO .
9.3.1
Logic Power Consumption
The following formula can be used to calculate the maximum core current consumption when the PLL is used depending on the frequency settings for the internal clocks: Icc = 3.45[mA/MHz] * CLKB[MHz] + 2.52[mA/MHz] * CLKP[MHz] + 0.72[mA/MHz] * CLKT[MHz] + 35.5 mA.
If clock modulation is used the following value must be added to this result: 0.24[mA/MHz] * CLKB[MHz]. This results in the following values: .
Maximum Core Current Consumption [mA] Logic Power Consumption PC at 5.25 V [mW]
Clock frequencies [MHz]
Remarks
CLKB 32 24 24 16 2 0.125
CLKP 16 24 12 16 2 0.125
CLKT 16 24 12 16 2 0.125 205 202 163 146 40 30 1.08 1.06 0.86 0.77 0.21 0.16 no PLL, no clock modulation no PLL, no clock modulation
Note: Higher frequency settings cannot be allowed in the package currently used. For higher frequency settings the maximum power consumption would exceed the maximum allowed value of 1.33W.
In addition to this power consumption of the MCU core logic the following contributions to the overall power consumption have to be considered:
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 36
10-Apr-01
9.3.2 Analog Power Consumption
Maximum Current Consumption
Module
Remarks
DAC ADC Power down reset Alarm Comparator
1 mA / channel 7 mA 0.5 mA 0.5 mA
To calculate the analog power consumption PA, the current contributions of the active modules have to be multiplied by the maximum analog supply voltage of 5.1 V.
9.3.3 I/O Power Consumption
I/O Buffers: The power dissipation (PIO) (at 5.25 V) of the I/O buffers is represented as the sum of the dynamic power dissipation (PAC) and the static power consumption (PDC). PIO = PAC * 1.1 + PDC The following table lists values for PAC:
Buffer Type
Power Consumption
Unit
Normal Input 12.4 Bidirectional Input 4 mA Bidirectional Output 194 + 25 CL 4 mA Output 8 mA Bidirectional Output 353 + 25 CL 8 mA Output PAC = PIB * In * f * operating rate + POB * On * f * operating rate PIB: POB: In: On: f: Operating rate: Power Consumption of Input Buffers and Bidirectional Inputs Power Consumption of Output Buffers and Bidirectional Outputs Total number of input buffers and bidirectional buffer inputs Total number of output buffers and bidirectional buffer outputs System frequency 1.0 if all buffers are switched simultaneously at system frequency W/MHz @ 5.0V
PDC is the caused by off chip loads which are drawing static currents. PDC = VO * IO * DCN FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 37 10-Apr-01
VO: IO: DCN:
Output voltage drop - usually 0.4 V Output current - usually 4 mA Number of output buffers and bidirectional buffers driving off chip loads causing static currents.
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 38
10-Apr-01
9.4
Converter Characteristics
* A/D Converter
Parameter Resolution Conversion error Non-linearity Differential Non-linearity Zero Reading voltage Full scale reading voltage Input current (VDDA) Reference voltage current
Symbol Minimum
Rating Typical
Unit Maximum 10 +/- 5.0 +/-2.5 +/-1.9 Bit LSB LSB LSB LSB LSB mA mA
Remark
overall error
V0T VFST IA IR
AVRL -3.5 AVRH-5.5
AVRL+0.5 AVRH-1.5 3.0 1.6
AVRL+4.5 AVRH+2.5 7.0 2.6
9.5
Clock settings
Clock name Max. frequency 64 MHz Core CLKB 32 MHz for supply voltage between 4.25 and 3.5 V Remark for supply voltage between 4.25 and 5.25 V
Clock domain
Resource bus Ext. Bus Clock for CAN
CLKP CLKT CANCLK
32 MHz 32 MHz 32 MHz
Note: Because of the maximum allowed current consumption setting all clocks to their maximum values is not possible in the current package. See calculation of power consumption above. However, clock modulation up to the frequencies specified above is still possible. In the case of modulation over 58 MHz no odd division factor (3,5,7,9,11,13) for CLKT must be selected.
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 39
10-Apr-01
9.6
Clock modulator settings
The clock modulator is a module to reduce EME (Electromagnetic Emission) problems by spreading the energy of the system over a wide range of the frequency spectrum. In order to allow optimization of system performance versus EME reduction, the modulator is programmable over a wide modulation range.
Clock Modulator ON ON ON
Input Frequency [MHz] 32 24 16
Number of operational settings for Clock Modulator 8 11 14
Detailed information about Clock Modulator operation and settings is available from Fujitsu on request.
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 40
10-Apr-01
Appendix A I/O Map
Version 1.3, 2000/02/28
Table A lists the addresses for the registers used by the internal peripheral functions of the MB91F367GA/F368GA.
* How to Read the I/O Map
Register Address +0 000014H PDRG [R/W]
XXXXXXXX
+1 PDRH [R/W]
XXXXXXXX
+2 PDRI [R/W]
----XXXX
+3 --
Internal peripheral Port data register
Read/write attribute Register initial value after a reset (bit initial values) "1": initial value "1", "0": initial value "0", "x": initial value "X" (indeterminate), "--" indicates non-existent bits Register name (The register in column 1 is at location 4n, the register in column 2 at 4n+1, and so on.) Location of far left of register (+0). +1, +2, and +3 each increment the location by one. When performing word access, the register in column 1 is placed at the MSB end of the data. Precautions: * Do not use RMW instructions on registers containing write-only (W) bits.
RMW instructions(RMW:read-modify-write) AND Rj, @Ri ANDH Rj, @Ri ANDB Rj, @Ri BANDL #u4, @Ri BANDH #u4, @Ri OR Rj, @Ri EOR Rj, @Ri EORH Rj, @Ri EORB Rj, @Ri BEORL #u4, @Ri BEORH #u4, @Ri ORH Rj, @Ri ORB Rj, @Ri BORL #u4, @Ri BORH #u4, @Ri
*
The data in reserved areas and areas marked "" is indeterminate. Do not use those areas!
Register Address +0
000000H 000004H 000008H 00000CH
Block +1
Reserved Reserved Reserved Reserved
+2
+3
T-unit Port Data Register
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10-Apr-01
Register Address +0
000010H 000014H 000018H 00001CH 000020H | 00003CH 000040H 000044H 000048H 00004CH 000050H 000054H 000058H 00005CH 000060H 000064H 000068H 00006CH 000070H 000074H 000078H 00007CH 000080H EIRR [R/W] 00000000 DICR [R/W] -------0 ENIR [R/W] 00000000 HRCL [R/W] 0 - - 11111 ELVR [R/W] 00000000 00000000 CLKR2 [R/W] - - - - - - 000 reserved PDRG [R/W] XXXXXXXX PDRK [R/W] XXXXXXXX PDRO [R/W] XXXXXXXX PDRS [R/W] XXXXXXXX Reserved
Block +1
PDRH [R/W] XXXXXXXX PDRL [R/W] XXXXXXXX PDRP [R/W] - - XXXXX
+2
PDRI [R/W] X---X--PDRM [R/W] - - - - XXXX PDRQ [R/W] - - XXXXX
+3
PDRJ [R/W] XXXXXXXX PDRN [R/W] - - XXXXXX PDRR [R/W] XXXXXXXX R-bus Port Data Register
Ext int/NMI DLYI/I-unit RTC Reload Timer 0
TMRLR0 [W] XXXXXXXX XXXXXXXX ________ TMRLR1 [W] XXXXXXXX XXXXXXXX ________ TMRLR2 [W] XXXXXXXX XXXXXXXX ________ SSR0 [R/W] 00001 - 00 ULS0 [R/W] - - - - 0000 UTIM0/UTIMR0 [R/W] 00000000 00000000 SIDR0 [R/W] XXXXXXXX
TMR0 [R] XXXXXXXX XXXXXXXX TMCSR0 [R/W] - - - - 0000 - - - 00000 TMR1 [R] XXXXXXXX XXXXXXXX TMCSR1 [R/W] - - - - 0000 - - - 00000 TMR2 [R] XXXXXXXX XXXXXXXX TMCSR2 [R/W] - - - - 0000 - - - 00000 SCR0 [R/W] 00000100 SMR0 [R/W] 00 - - 0 - 0 -
Reload Timer 1
Reload Timer 2
UART0
DRCL0 [W] -------________
UTIMC0 [R/W] 0 - - - 0 - 01
U-TIMER 0 Reserved
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 42
10-Apr-01
Register Address +0
000084H
Block +1 +2 +3
SIO 0 SES0 [R/W] - - - - - - 00 SES1 [R/W] - - - - - - 00 CDCR1 [R/W] 0 - - - 1111 SDR0 [R/W] 00000000 SDR1 [R/W] 00000000 Reserved SIO 1 SIO 0/1 Prescaler Reserved IBCR [R/W] 00000000 IBSR [R] 00000000 IDAR [R/W] XXXXXXXX ADMD [R/W,W] - - - X0000 ADCH [R/W] 00000000 IADR [R/W] -XXXXXXX ICCR [R/W] - - 0XXXXX IDBL [R/W] -------0 ADCS [R/W,W] 0000 - - 00 ADBL [R/W] -------0 ________ ________ IOTDBL0 [R/W] - - - - - 000 ICS01 [R/W] 00000000 IOTDBL1 [R/W] - - - - - 000 ICS23 [R/W] 00000000 Input Capture 0,1,2,3 Reserved I2C (old) -> new I2C from address 0x184 A/D Converter SMCS0 [R/W] 00000010 - - - - 00-0
000088H 00008CH 000090H 000094H 000098H
SMCS1 [R/W] 00000010 - - - - 00 - 0 CDCR0 [R/W] 0 - - - 1111 Reserved
00009CH 0000A0H 0000A4H 0000A8H 0000ACH 0000B0H 0000B4H 0000B8H 0000BCH 0000C0H 0000C4H 0000C8H
ADCD [R/W] 000000XX XXXXXXXX
IPCP0 [R] XXXXXXXX XXXXXXXX IPCP2 [R] XXXXXXXX XXXXXXXX OCS01 [R/W] - - - 0 - - 00 0000 - - 00 OCCP0 [R/W] XXXXXXXX XXXXXXXX ________
IPCP1 [R] XXXXXXXX XXXXXXXX IPCP3 [R] XXXXXXXX XXXXXXXX reserved OCCP1 [R/W] XXXXXXXX XXXXXXXX Output Compare 0,1
Reserved
TCDT0 [R/W] XXXXXXXX XXXXXXXX TCDT1 [R/W] XXXXXXXX XXXXXXXX
________
TCCS0 [R/W] - 0000000 TCCS1 [R/W] - 0000000
Free Running Counter 0 for ICU/OCU Free Running Counter 1 for ICU/OCU
0000CCH
________
0000D0H
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 43
10-Apr-01
Register Address +0
0000D4H 0000D8H 0000DCH 0000E0H 0000E4H 0000E8H 0000ECH 0000F0H 0000F4H 0000F8H 0000FCH 000100H 000104H 000108H 00010CH 000110H 000114H 000118H 00011CH 000120H 000124H 000128H 00012CH 000130H 000134H PTMR0 [R] 11111111 11111111 PDUT0 [W] XXXXXXXX XXXXXXXX PTMR1 [R] 11111111 11111111 PDUT1 [W] XXXXXXXX XXXXXXXX PTMR2 [R] 11111111 11111111 PDUT2 [W] XXXXXXXX XXXXXXXX GCN10 [R/W] 00110010 00010000 PDBL0 [R/W] - - - 00000 ________ PCSR0 [W] XXXXXXXX XXXXXXXX PCNH0 [R/W] 0000000 PCNL0 [R/W] 000000 - 0 PWM1 GCN20 [R/W] - - - - 0000 PWM Control 0 Reserved PWM0 WTHR [R/W] - - - 00000 WTDBL [R/W] -------0 WTCR [R/W] 00000000 000 - 0000 Real Time Clock (WatchTimer)
Block +1
________
+2
+3
Reserved
WTBR [R/W] - - XXXXXX XXXXXXXX XXXXXXXX WTMR [R/W] - - 000000 WTSR [R/W] - - 000000
________
Reserved
PCSR1 [W] XXXXXXXX XXXXXXXX PCNH1 [R/W] 0000000 PCNL1 [R/W] 000000 - 0
PCSR2 [W] XXXXXXXX XXXXXXXX PCNH2 [R/W] 0000000 PCNL2 [R/W] 000000 - 0
PWM2
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 44
10-Apr-01
Register Address +0
000138H 00013CH 000140H 000144H 000148H 00014CH 000150H 000154H 000158H 00015CH 000160H 000164H 000168H 00016CH 000170H 000174H 000178H 00017CH 000180H 000184H 000188H 00018CH 000190H 000194H ACCDBL[R/W] -------0
IBCR2 [R/W]
Block +1 +2 +3
PWM3 PTMR3 [R] 11111111 11111111 PDUT3 [W] XXXXXXXX XXXXXXXX PCSR3 [W] XXXXXXXX XXXXXXXX PCNH3 [R/W] 0000000 ________ PCNL3 [R/W] 000000 - 0 Reserved
CMCR [R/W] 11111111 0000000 CMLS0 [R/W] 01110111 1111111 CMLS2 [R/W] 01110111 1111111 CMLT0 [R/W] -----100 00000010 CMLT2 [R/W] -----100 00000010 CMAC [R/W] 11111111 1111111 PDRCR [R/W] - - - - - 000 ACSR [R/W] - - - XXX00
IBSR2 [R] 00000000 ITMKL [R/W]
CMPR [R/W] ----1001 1---0001 CMLS1 [R/W] 01110111 1111111 CMLS3 [R/W] 01110111 1111111 CMLT1 [R/W] 11110100 00000010 CMLT3 [R/W] -----100 00000010 CMTS [R/W] --000001 01111111
Clock Modulation
Power down reset Alarm comparator
ITBAH [R/W]
00000000
ITMKH [R/W]
- - - - - - 00
ISMK [R/W]
ITBAL [R/W] 00000000
ISBA [R/W]
I2C (new)
00 - - - - 11
IDARH [-] 00000000
11111111
IDAR2 [R/W]
01111111
ICCR2 [R/W]
- 0000000 IDBL2(*) [R/W] -------0
00000000
- 0011111
(*) old and new I2C share this bit! calibration unit of 32KHz oscillator (only on F368GA)
CUCR [R/W] - - - - - - - - - - - 0 - -00 CUTR1 [R] -------- 00000000
CUTD [R/W] 10000000 00000000 CUTR2 [R] 00000000 00000000
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 45
10-Apr-01
Register Address +0
000198H | 0001F8H 0001FCH 000200H 000204H 000208H 00020CH 000210H 000214H 000218H 00021CH 000220H 000224H 000228H | 00023CH 000240H 000244H | 0003ECH 0003F0H 0003F4H 0003F8H 0003FCH
Block +1
-----1 Reserved F362MD [R/W] 00000000 DMACA0 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB0 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMACA1 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB1 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMACA2 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB2 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMACA3 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB3 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMACA4 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX ________ F362 Mode Reg DMAC
+2
+3
DMACR [R/W] 00--0000 -------- -------- -------________ Reserved
BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Bit Search Module
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 46
10-Apr-01
Register Address +0
000400H 000404H 000408H 00040CH 000410H 000414H 000418H 00041CH 000420H | 00043CH DDRG [R/W] 00000000 DDRK [R/W] 00000000 DDRO [R/W] 00000000 DDRS [R/W] 00000000 PFRG [R/W] 00000000 PFRK [R/W] 00000000 PFRO [R/W] 00000000 PFRS [R/W] 00000000 ________ Reserved PFRH [R/W] 00000000 PFRL [R/W] 00000000 PFRP [R/W] 00000000 PFRI [R/W] ----0--PFRM [R/W] ----0000 PFRQ [R/W] --000000 PFRJ [R/W] 00000000 PFRN [R/W] --000000 PFRR [R/W] 00000000 R-bus Port Function Register
Block +1
DDRH [R/W] 00000000 DDRL [R/W] 00000000 DDRP [R/W] ----0000
+2
DDRI [R/W] ----0--DDRM [R/W] ----0000 DDRQ [R/W] --000000
+3
DDRJ [R/W] 00000000 DDRN [R/W] --000000 DDRR [R/W] 00000000 R-bus Port Direction Register
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 47
10-Apr-01
Register Address +0
000440H 000444H 000448H 00044CH 000450H 000454H 000458H 00045CH 000460H 000464H 000468H 00046CH 000470H | 00047CH 000480H 000484H 000488H | 0005FCH 000600H 000604H 000608H 00060CH RSRR [R/W] 10000000 CLKR [R/W] 00000000 ICR00 [R/W] ---11111 ICR04 [R/W] ---11111 ICR08 [R/W] ---11111 ICR12 [R/W] ---11111 ICR16 [R/W] ---11111 ICR20 [R/W] ---11111 ICR24 [R/W] ---11111 ICR28 [R/W] ---11111 ICR32 [R/W] ---11111 ICR36 [R/W] ---11111 ICR40 [R/W] ---11111 ICR44 [R/W] ---11111
Block +1
ICR01 [R/W] ---11111 ICR05 [R/W] ---11111 ICR09 [R/W] ---11111 ICR13 [R/W] ---11111 ICR17 [R/W] ---11111 ICR21 [R/W] ---11111 ICR25 [R/W] ---11111 ICR29 [R/W] ---11111 ICR33 [R/W] ---11111 ICR37 [R/W] ---11111 ICR41 [R/W] ---11111 ICR45 [R/W] ---11111
+2
ICR02 [R/W] ---11111 ICR06 [R/W] ---11111 ICR10 [R/W] ---11111 ICR14 [R/W] ---11111 ICR18 [R/W] ---11111 ICR22 [R/W] ---11111 ICR26 [R/W] ---11111 ICR30 [R/W] ---11111 ICR34 [R/W] ---11111 ICR38 [R/W] ---11111 ICR42 [R/W] ---11111 ICR46 [R/W] ---11111
+3
ICR03 [R/W] ---11111 ICR07 [R/W] ---11111 ICR11 [R/W] ---11111 ICR15 [R/W] ---11111 ICR19 [R/W] ---11111 ICR23 [R/W] ---11111 ICR27 [R/W] ---11111 ICR31 [R/W] ---11111 ICR35 [R/W] ---11111 ICR39 [R/W] ---11111 ICR43 [R/W] ---11111 ICR47 [R/W] ---11111 Interrupt Control unit
________
STCR [R/W] 00110011 WPR [W] XXXXXXXX
TBCR [R/W] X0000X00 DIVR0 [R/W] 00000011
CTBR [W] XXXXXXXX DIVR1 [R/W] 00000000
Clock Control unit
________
Reserved
________
Reserved
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 48
10-Apr-01
Register Address +0
000610H 000614H 000618H 00061CH 000620H 000624H 000628H | 00063F H 000640H 000644H 000648H 00064CH 000650H 000654H 000658H 00065CH 000660H 000664H 000668H 00066CH 000670H 000674H | 0007F8H 0007FCH ________ CHE 11111111 ASR0 [W] 00000000 00000000 ASR1 [W] 00000000 00000000 ASR2 [W] 00000000 00000000 ASR3 [W] 00000000 00000000 ASR4 [W] 00000000 00000000 ASR5 [W] 00000000 00000000 ASR6 [W] 00000000 00000000 ASR7 [W] 00000000 00000000 AMD0 [R/W] -00XX111 AMD4 [R/W] --XXXXXX CSE 11000011 ________ ________ ________ AMD1 [R/W] -XXXXXXX AMD5 [R/W] --XXXXXX ________ ________ Reserved ________
Block +1 +2 +3
Reserved
AMR0 [W] 11111000 11111111 AMR1 [W] 00000000 00000000 AMR2 [W] 00000000 00000000 AMR3 [W] 00000000 00000000 AMR4 [W] 00000000 00000000 AMR5 [W] 00000000 00000000 AMR6 [W] 00000000 00000000 AMR7 [W] 00000000 00000000 AMD2 [R/W] --XXXXXX AMD6 [R/W] -XXXXXXX ________ AMD3 [R/W] --XXXXXX AMD7 [R/W] -XXXXXXX ________ ________ ________
T-unit
Reserved
MODR [W] XXXXXXXX
________
________
Mode Register
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 49
10-Apr-01
Register Address +0
000800H | 000B6CH 001000H 001004H 001008H 00100CH 001010H 001014H 001018H 00101CH 001020H 001024H 001028H | 003FFCH 004000H | 006FFFH 007000H 007004H 007008H | 00FFFCH 010000H | 010FFCH FMCS [R/W] 1110X000 FMWT [R/W] --000011 ________ ________ ________
Block +1
________
+2
+3
Reserved
DMASA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ________
DMAC
Reserved
________
Reserved
________ ________
________ ________
Flash Memory Control Register Reserved
________ Reserved
011000H | 011FFCH
________
I-RAM 4 kB
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 50
10-Apr-01
Register Address +0
012000H | 01FFFCH 020000H | 03BFFCH 03C000H | 03FFFCH 040000H | 043FFCH 044000H | 0FEFFC 050000H | 0507FCH 050800H | 07FFF4H 080000H | 09FFFCH 0A0000H | 0BFFFC 0C0000H | 0DFFFC 0E0000H | 0EFFFC 0F0000H | 0F3FFCH 0F4000H | 0F7FFCH 0F8000H | 0FFFF4H Sector 0 64 KB Sector 1 64 KB Sector 2 64 KB Sector 3 32 KB Sector 4 8 KB Sector 5 8 KB Sector 6 16 KB ________ reserved Sector 7 64 KB Sector 8 64 KB Sector 9 64 KB Sector 10 32 KB Sector 11 8 KB Sector 12 8 KB Sector 13 16 KB Flash Memory 512 K on F-Bus ________ Reserved Boot ROM 2 kB (F-Bus)
Block +1
________
+2
+3
Reserved
________
Reserved
User RAM 16 kB (D-Bus) Fast RAM 16 kB (F-Bus)
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 51
10-Apr-01
Register Address +0
0FFFF8H 0FFFFCH
Block +1
FMV [R] 06 00 00 00H FRV [R] 00 05 00 00H
+2
+3
Fixed Reset/Mode Vector
Write operations to address 0FFFF8H and 0FFFFCH are not possible. When reading these addresses, the values shown above will be read.
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 52
10-Apr-01
Register Address +0
100000H 100004H 100008H 10000CH 100010H 100014H 100018H 10001CH 100020H 100024H 100028H 10002CH | 100048H 10004CH 100050H 100054H 100058H 10005CH 100060H 100064H
Block +1 +2 +3
CAN 0 Remark: Address range for CAN 0 to CAN 1 depends on chip select range. Mentioned addresses are default values, determined by boot ROM contents. BVALR0 [R/W] 00000000 00000000 TCANR0 [W] 00000000 00000000 RCR0 [R/W] 00000000 00000000 ROVRR0 [R/W] 00000000 00000000 CSR0 [R/W] 00000000 00000001 RTEC0 [R] 00000000 00000000 IDER0 [R/W] XXXXXXXX XXXXXXXX RFWTR0 [R/W] XXXXXXXX XXXXXXXX TREQR0 [R/W] 00000000 00000000 TCR0 [R/W] 00000000 00000000 RRTRR0 [R/W] 00000000 00000000 RIER0 [R/W] 00000000 00000000 LEIR0 [R/W] 000-0000 BTR0 [R/W] -1111111 11111111 TRTRR0 [R/W] 00000000 00000000 TIER0 [R/W] 00000000 00000000
AMSR0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX AMR00 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX AMR10 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX GENERAL PURPOSE RAM [R/W]
IDR00 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR10 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR20 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR30 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR40 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR50 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR60 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 53
10-Apr-01
Register Address +0
100068H 10006CH 100070H 100074H 100078H 10007CH 100080H 100084H 100088H 10008CH 100090H 100094H 100098H 10009CH 1000A0H 1000A4H 1000A8H 1000ACH
Block +1 +2 +3
CAN 0 IDR70 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR80 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR90 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR100 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR110 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR120 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR130 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR140 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR150 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX DLCR00 [R/W] -------- ----XXXX DLCR20 [R/W] -------- ----XXXX DLCR40 [R/W] -------- ----XXXX DLCR60 [R/W] -------- ----XXXX DLCR80 [R/W] -------- ----XXXX DLCR100 [R/W] -------- ----XXXX DLCR120 [R/W] -------- ----XXXX DLCR140 [R/W] -------- ----XXXX DLCR10 [R/W] -------- ----XXXX DLCR30 [R/W] -------- ----XXXX DLCR50 [R/W] -------- ----XXXX DLCR70 [R/W] -------- ----XXXX DLCR90 [R/W] -------- ----XXXX DLCR110 [R/W] -------- ----XXXX DLCR130 [R/W] -------- ----XXXX DLCR150 [R/W] -------- ----XXXX
DTR00 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR10 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1000B4H
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 54
10-Apr-01
Register Address +0
1000BCH
Block +1 +2 +3
CAN 0 DTR20 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR30 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR40 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR50 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR60 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR70 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR80 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR90 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR100 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR110 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR120 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR130 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR140 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR150 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX CREG0 [R/W] 00000000 00000110
1000C4H
1000CCH
1000D4H
1000DCH
1000E4H
1000ECH
1000F4H
1000FCH
100104H
10010CH
100114H
10011CH
100124H
10012CH
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 55
10-Apr-01
Register Address +0
100200H 100204H 100208H 10020CH 100210H 100214H 100218H 10021CH 100220H 100224H 100228H 10022CH | 100248H 10024CH 100250H 100254H 100258H 10025CH 100260H 100264H
Block +1 +2 +3
CAN 1 Remark: Address range for CAN 0 to CAN 1 depends on chip select range. Mentioned addresses are default values, determined by boot ROM contents. BVALR1 [R/W] 00000000 00000000 TCANR1 [W] 00000000 00000000 RCR1 [R/W] 00000000 00000000 ROVRR1 [R/W] 00000000 00000000 CSR1 [R/W] 00000000 00000001 RTEC1 [R] 00000000 00000000 IDER1 [R/W] XXXXXXXX XXXXXXXX RFWTR1 [R/W] XXXXXXXX XXXXXXXX TREQR1 [R/W] 00000000 00000000 TCR1 [R/W] 00000000 00000000 RRTRR1 [R/W] 00000000 00000000 RIER1 [R/W] 00000000 00000000 LEIR1 [R/W] 000-0000 BTR1 [R/W] -1111111 11111111 TRTRR1 [R/W] 00000000 00000000 TIER1 [R/W] 00000000 00000000
AMSR1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX AMR01 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX AMR11 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX GENERAL PURPOSE RAM [R/W]
IDR01 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR11 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR21[R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR31 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXXIDR41 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR51 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR61 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 56
10-Apr-01
Register Address +0
100268H 10026CH 100270H 100274H 100278H 10027CH 100280H 100284H 100288H 10028CH 100290H 100294H 100298H 10029CH 1002A0H 1002A4H 1002A8H 1002ACH
Block +1 +2 +3
CAN 1 IDR71 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR81 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR91 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR101 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR111 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR121 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXX--IDR131 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR141 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX IDR151 [R/W] XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX DLCR01 [R/W] -------- ----XXXX DLCR21 [R/W] -------- ----XXXX DLCR41 [R/W] -------- ----XXXX DLCR61 [R/W] -------- ----XXXX DLCR81[R/W] -------- ----XXXX DLCR101 [R/W] -------- ----XXXX DLCR121 [R/W] -------- ----XXXX DLCR141 [R/W] -------- ----XXXX DLCR11 [R/W] -------- ----XXXX DLCR31 [R/W] -------- ----XXXX DLCR51 [R/W] -------- ----XXXX DLCR71 [R/W] -------- ----XXXX DLCR91 [R/W] -------- ----XXXX DLCR111 [R/W] -------- ----XXXX DLCR131 [R/W] -------- ----XXXX DLCR151 [R/W] -------- ----XXXX
DTR01 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR11 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1002B4H
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 57
10-Apr-01
Register Address +0
1002BCH
Block +1 +2 +3
CAN 1 DTR21 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR31 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR41 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR51 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR61 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR71 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR81 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR91 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR101 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR111 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR121 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR131 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR141 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTR151 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX CREG1 [R/W] 00000000 00000110
1002C4H
1002CCH
1002D4H
1002DCH
1002E4H
1002ECH
1002F4H
1002FCH
100304H
10030CH
100314H
10031CH
100324H
10032CH
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 58
10-Apr-01
Appendix B Interrupt Vectors
This appendix lists the interrupt vector table. The interrupt vector table lists the interrupt vectors and interrupt control registers assigned to each MB91360 interrupt.
Interrupt number Interrupt Decimal Reset *6 Mode vector *6 System reserved System reserved System reserved System reserved System reserved Co-processor fault trap *4 Co-processor error trap *4 INTE instruction *4 Instruction break exception *4 Operand break trap *4 Step trace trap *4 NMI interrupt(tool)*4 Undefined instruction exception NMI request External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Hexadecimal 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16
Interrupt level*1 Setting Register FH fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 0x440 0x441 0x442 0x443 0x444 0x445 0x446 Register address -
Interrupt vector*2 Offset 0x3FC 0x3F8 0x3F4 0x3F0 0x3EC 0x3E8 0x3E4 0x3E0 0x3DC 0x3D8 0x3D4 0x3D0 0x3CC 0x3C8 0x3C4 0x3C0 0x3BC 0x3B8 0x3B4 0x3B0 0x3AC 0x3A8 0x3A4 Default Vector address 0x000FFFFC 0x000FFFF8 0x000FFFF4 0x000FFFF0 0x000FFFEC 0x000FFFE8 0x000FFFE4 0x000FFFE0 0x000FFFDC 0x000FFFD8 0x000FFFD4 0x000FFFD0 0x000FFFCC 0x000FFFC8 0x000FFFC4 0x000FFFC0 0x000FFFBC 0x000FFFB8 0x000FFFB4 0x000FFFB0 0x000FFFAC 0x000FFFA8 0x000FFFA4 4 5 8 9 RN
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 59
10-Apr-01
External Interrupt 7 Reload Timer 0 Reload Timer 1 Reload Timer 2 CAN 0 RX CAN 0 TX/NS CAN 1 RX CAN 1 TX/NS CAN 2 RX 7 CAN 2 TX/NS7 CAN 3 RX 5 CAN 3 TX/NS 5 PPG 0/1 PPG 2/3 PPG 4/57 PPG 6/77 Reload Timer 37 Reload Timer 47 Reload Timer 57 ICU 0/1 OCU 0/1 ICU 2/3 OCU 2/37 ADC Timebase Overflow Free Running Counter 0 Free Running Counter 1 SIO 0 SIO 1 Sound Generator7 UART 0 RX UART 0 TX UART 1 RX7 UART 1 TX7
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38
ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40
0x447 0x448 0x449 0x44A 0x44B 0x44C 0x44D 0x44E 0x44F 0x450 0x451 0x452 0x453 0x454 0x455 0x456 0x457 0x458 0x459 0x45A 0x45B 0x45C 0x45D 0x45E 0x45F 0x460 0x461 0x462 0x463 0x464 0x465 0x466 0x467 0x468
0x3A0 0x39C 0x398 0x394 0x390 0x38C 0x388 0x384 0x380 0x37C 0x378 0x374 0x370 0x36C 0x368 0x364 0x360 0x35C 0x358 0x354 0x350 0x34C 0x348 0x344 0x340 0x33C 0x338 0x334 0x330 0x32C 0x328 0x324 0x320 0x31C
0x000FFFA0 0x000FFF9C 0x000FFF98 0x000FFF94 0x000FFF90 0x000FFF8C 0x000FFF88 0x000FFF84 0x000FFF80 0x000FFF7C 0x000FFF78 0x000FFF74 0x000FFF70 0x000FFF6C 0x000FFF68 0x000FFF64 0x000FFF60 0x000FFF5C 0x000FFF58 0x000FFF54 0x000FFF50 0x000FFF4C 0x000FFF48 0x000FFF44 0x000FFF40 0x000FFF3C 0x000FFF38 0x000FFF34 0x000FFF30 0x000FFF2C 0x000FFF28 0x000FFF24 0x000FFF20 0x000FFF1C 0 1 2 3 14 6 7
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 60
10-Apr-01
UART 2 RX7 UART 2 TX7 I2C Alarm Comparator RTC / Calibration 8 (Watchtimer) DMA Delayed interrupt activation bit System reserved *3 System reserved *3 Security vector System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Used by the INT instruction.
57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 to 255
39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 to FF
ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 -
0x469 0x46A 0x46B 0x46C 0x46D 0x46E 0x46F -
0x318 0x314 0x310 0x30C 0x308 0x304 0x300 0x2FC 0x2F8 0x2F4
0x000FFF18 0x000FFF14 0x000FFF10 0x000FFF0C 0x000FFF08 0x000FFF04 0x000FFF00 0x000FFEFC 0x000FFEF8 0x000FFEF4 0x000FFEF0 0x000FFEEC 0x000FFEE8 0x000FFEE4 0x000FFEE0 0x000FFEDC 0x000FFED8 0x000FFED4 0x000FFED0 0x000FFECC 0x000FFEC8 0x000FFEC4 0x000FFEC0 0x000FFEBC to 0x000FFC00
10 11 13
(ICR51) (ICR52) (ICR53) (ICR54) (ICR55) (ICR56) (ICR57) (ICR58) (ICR59) (ICR60) (ICR61) (ICR62) (ICR63) -
0x473 0x474 0x475 0x476 0x477 0x478 0x479 0x47A 0x47B 0x47C 0x47D 0x47E 0x47F -
0x2F0 0x2EC 0x2E8 0x2E4 0x2E0 0x2DC 0x2D8 0x2D4 0x2D0 0x2CC 0x2C8 0x2C4 0x2C0 0x2BC to 0x000
The ICRs are located in the interrupt controller and set the interrupt level for each interrupt request. An ICR is provided for each interrupt request. *2 The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the table base register value (TBR). The TBR specifies the top of the EIT vector table. The addresses listed in the table are for the default TBR value (0x000FFC00). The TBR is initialized to this value by a reset.After execution of the internal boot ROM TBR is set to 0x00FFC00.
*3 *4
*1
Used by REALOS System reserved *5 Only available on MB91V360/MB91FV360 *6 Mode and reset vector cannot be changed, for their contents see IO map *7 not available on MB91F367GA/F368GA FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 61 10-Apr-01
*8
calibration unit is not available on F365G
Remarks: The 1-Kbyte area from the address specified in TBR is the EIT vector area. Each vector consists of four bytes. The following formula shows the relationship between the vector number and vector address. vctadr=TBR + vctofs = TBR + (3FCH - 4 x vct) vctadr:Vector address vctofs:Vector offset vct:Vector number
FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 62
10-Apr-01

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